Shinichi Nishizawa

Publications

Journals (15)

  1. Shinichi Nishizawa, Shinji Kimura, "Standard Cell Structure and Diffusion Reordering for Block Area Reduction in Double Diffusion Break FinFET Process," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E108-A,No.6,pp.-,Jun. 2025.
  2. Shinichi Nishizawa, Masahiro Matsuda, Shinji Kimura, "Multithread Implementation for Open Cell Timing Characterizer," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E108-A,No.3,pp.-,Mar. 2025.
  3. Shinichi Nishizawa, Toru Nakura, "libretto: An Open Cell Timing Characterizer for Open Source VLSI Design," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E106-A, No. 3, pp.551-559, March 2023.
  4. Shinichi Nishizawa, Shih-Ting Lin, Yih-Lang Li, Hidetoshi Onodera, "Supplemental PDK for ASAP7 using Synopsys Flow," IPSJ Transactions on System LSI Design Methodology (T-SLDM), Vol. 14, pp. 24-26, March 2021.
  5. Shinichi Nishizawa, Hidetoshi Onodera, "Design Methodology for Variation Tolerant D-Flip-Flop using Regression Analysis," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E-101, No, 12, pp.2222-2230, December 2018.
  6. Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera, "Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell," IPSJ Transactions on System LSI Design Methodology, Vol. 8, pp 131-135, August, 2015.
  7. Shinichi Nishizawa, Tohru Ishihara and Hidetoshi Onodera, "Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E96-A, No 12, pp. 2499-2504, December, 2013
  8. Shinichi Nishizawa and Hidetoshi Onodera, "A Ring Oscillator with Calibration Circuit for On-Chip Measurement of Static IR-drop" , IEEE Transactions on Semiconductor Manufacturing, Vol. 26, Issue 3, pp. 306-313, August, 2013
  1. Ruilin Zhang, Haochen Zhang, Xingyu Wang, Ye Ziyang, Kunyang Liu, Shinichi Nishizawa, Kiichi Niitsu, and Hirofumi Shinohara, "De-correlation and De-bias Post-processing Circuits for True Random Number Generator," IEEE Transactions Circuits and Systems-I: Regular Papers, 2024, 13-pages.
  2. Mingtao Zhang, Shinichi Nishizawa, Shinji Kimura, "Area Efficient Approximate 4-2 Compressor and Probability-based Error Adjustment for Approximate Multiplier," IEEE Transactions on Circuits and Systems II: Express Briefs，Vol. 70, Issue 5, pp.1714-1718, May 2023.
  3. Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen, and Hidetoshi Onodera, "NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 41, Issue 12, pp.5568 - 5581, December 2022.
  4. Yuki Imai, Shinichi Nishizawa, Kazuhito Ito, "Reduction of LSI Maximum Power Consumption with Standard Cell Library of Stack Structured Cells," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E105.A, No. 3 , pp. 487-496, December 2021.
  5. Takumi Hosaka, Shinichi Nishizawa, Ryo Kishida, Takashi Matsumoto, Kazutoshi Kobayashi, "Universal NBTI Compact Model Replicating AC Stress / Recovery from a Single-shot Long-term DC Measurement, " IPSJ Transactions on System LSI Design Methodology, Vol. 13, pp 56-64, 2020.
  6. Kota Chubachi, Shinichi Nishizawa, Kazuhito Ito, "Analog circuit design methodology utilizing a structure of thin BOX FDSOI", IEICE Electronics Express (ELEX), Vol.16, No.5, pp.1–7, 2019
  7. Kazuhito Ito, Yuto Ishihara, Shinichi Nishizawa, "Minimization of Vote Operations for Soft Error Detection in DMR Design with Error Correction by Operation Re-Execution", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E-101, No, 12, pp.2271-2279, December 2018.

International Conferences (37)

  1. Shinichi Nishizawa, Shinji Kimura, "Standard Cell Structure and Transistor Reordering for Mitigating Area Penalty in Double Diffusion Break FinFET Process," International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA), 4-pages, April, 2024, Taiwan.
  2. Shinichi Nishizawa and Toru Nakura, "Library characterizer for open-source VLSI design," The Workshop on Open-Source EDA Technology (WOSET), 4-pages, November, 2022, USA (Online).
  3. Shinichi Nishizawa and Toru Nakura, "Density Aware Cell Library Design for Design-Technology Co-Optimization", International Symposium on Quality Electronic Design (ISQED), 2-pages, April 2022, USA .
  4. Shinichi Nishizawa and Kazuhito Ito, "Process Variation Estimation using An IDDQ Test and FlipFlop Retention Characteristics", International Conference on Microelectronic Test Structures (ICMTS), pp. 7-10, April 2020, UK (Online).
  5. Shinichi Nishizawa and Hidetoshi Onodera, "Process Variation Aware D-Flip-Flop Design using Regression Analysis", International Symposium on Quality Electronic Design (ISQED), pp.83-93, March 2018, USA.
  6. Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera, "An Impact of Process Variation on Supply Voltage Dependence of Logic Path Delay Variation," IEEE International Symposium on VLSI Design Automation and Test (VLSI-DAT), pp. 161-169, May 2015, Taiwan.
  7. Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera, "Design Methodology of Process Variation Tolerant D-Flip-Flops for Low Voltage Circuit Operation," IEEE International System-On-Chip Conference (SoCC), pp.42-47, September 2014, USA.
  8. Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera, "Variation Tolerant Design of D-Flip-Flops for Low Voltage Circuit Operation," International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 28-32, March 2014, USA.
  9. Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera, "An Impact of Within-Die Variation on Supply Voltage Dependence of Path Delay," International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 31-34, March 2013, USA.
  10. Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera, "Analysis and Comparison of XOR Cell Structures for Low Voltage Circuit Design," IEEE International Symposium on Quality Electronic Design (ISQED), pp. 719-725, March 2013, USA.
  11. Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera, "An Impact of Within-Die Variation on Supply Voltage Dependence of Path Delay," IEEE/ACM International Workshop on Variability Modeling and Characterization (VMC), November 2012, USA.
  12. Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera, "A Flexible Structure of Standard Cell and Its Optimization Method for Near-Threshold Voltage Operation," IEEE International Conference on Computer Design (ICCD), pp. 235-240, October 2012 ,Canada.
  13. Shinichi Nishizawa and Hidetoshi Onodera, "Ring Oscillator with Calibration Circuit for Accurate On-Chip IR-drop Measurement," IEEE International Conference on Microelectronics Test Structure (ICMTS), pp. 3-7, March 2012, USA.
  14. Shinichi Nishizawa and Hidetoshi Onodera, "Ring Oscillator with Calibration Circuit for Accurate On-Chip IR-drop Measurement," 5th GCOE International Symposium on Phonics and Electronics Science and Engineering, March 2012, Kyoto.
  15. Shinichi Nishizawa, Kazutoshi Kobayashi, Hidetoshi Onodera, "Variability Characterization Using an RO-array Test Structure and Its Impact on Design," IEEE workshop on Design for Manufacturability and Yield (DFM&Y), pp.7-10, June 2010, USA.
  1. Ke Ma, Shinichi Nishizawa, Shinji Kimura, "Exploring Training of Approximate CNNs using Straight-through and Linear-regression-based Gradient Estimation," International Symposium on System-on-Chip Conference (SOCC), 6-pages, September, 2025, U.A.E.. (to appear)
  2. Xinyi Guo, Geguang Miao, Shinichi Nishizawa, Hiromitsu Awano, Shinji Kimura, and Takashi Sato, "SOME: Symmetric One-Hot Matching Elector — A Lightweight Microsecond Decoder for Quantum Error Correction," International Conference on Computer-Aided Design (ICCAD), 6-pages, October, 2025, Germany. (to appear)
  3. Ryoma Katsube, Shinichi Nishizawa, Tomoaki Ukezono, "An EDA Based Side-Channel Attack Flamework for Netlists," SoutheastCon, 4-pages, April, 2025, Taiwan.
  4. Ruilin Zhang, Xiaoyang Jun, Jiawei Liu, Xingyu Wang, Shufan Xu, Kunyang Liu, Shinichi Nishizawa, Kiichi Niitsu, Hirofumi Shinohara, "A Latch-based Stochastic Number Generator for Stochastic Computing of Extended Naïve Bayesian," International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA), 4-pages, April, 2024, Taiwan.
  5. Mingtao Zhang, Ke Ma, Renrui Duan, Shinichi Nishizawa, Shinji Kimura, "Evaluation of Application-Independent Unbiased Approximate Multipliers for Quantized Convolutional Neural Networks," International Symposium on System-on-Chip Conference (SOCC), 6-pages, September 2023.
  6. Xinyi Guo, Geguang Miao, Shinichi Nishizawa, Shinji Kimura, "Prime Factorization Based on Multiple Quantum Annealings on Partial Constraints with Analytical Variable Reduction," International Symposium on System-on-Chip Conference (SOCC), 6-pages, September 2023.
  7. Zekun Wang, Shinichi Nishizawa, Shinji Kimura, "An 8-Point Approximate DCT Design with Optimized Signed Digit Encoding," International Symposium on System-on-Chip Conference (SOCC), 6-pages, September 2023.
  8. Renrui Duan, Mingtao Zhang, Yi Guo, Shinichi Nishizawa, Shinji Kimura, "A Hardware-Efficient Approximate Multiplier Combining Inexact Same-Weight N:2 Compressors and Remapping Logic with Error Recovery," International Symposium on System-on-Chip Conference (SOCC), 6-pages, September 2023.
  9. Mingtao Zhang, Shinichi Nishizawa, Shinji Kimura, "Area Efficient Approximate 4-2 Compressor and Probability-based Error Adjustment for Approximate Multiplier," International Symposium on Circuits and Systems (ISCAS), 5-pages, May 2023. (Invited to TCASII, removed from IEEE Xplore)
  10. Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa and Hidetoshi Onodera, "Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing," International Conference on Computer Aided Design (ICCAD), 8-pages, November 2020.
  11. Yuya Kitazawa, Shinichi Nishizawa, Kazuhito Ito, "Register Minimization in Double Modular Redundancy Design with Soft Error Correction by Replay," in Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), October 2019.
  12. Takumi Hosaka, Shinichi Nishizawa, Ryo Kishida, Takashi Matsumoto, Kazutoshi Kobayashi, "Compact Modeling of NBTI Replicating AC Stress / Recovery from a Single-shot Long-term DC Measurement," in International Online Testing Symposium (IOLTS), pp. 305-309, July 2019.
  13. Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen, Hidetoshi Onodera, "NCTUcell: A DDA-aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map," in Design Automation Conference (DAC), pp. 120:1-120:6, June 2019.
  14. A.K.M. Mahfuzul Islam, Shinichi Nishizawa, Yusuke Matsui, Yoshinobu Ichida, "Drive-Strength Selection for Synthesis of Leakage-Dominant Circuits", International Symposium on Quality Electronic Design (ISQED), pp.298-303, May 2019.
  15. Takuma Konno, Shinichi Nishizawa, Kazuhito Ito, "Process Variation Estimation using A Combination of Ring Oscillator Delay and FlipFlop Retention Characteristics", International Conference on Microelectronic Test Structures (ICMTS), pp.97-101, May 2018.
  16. Hong-Yan Su, Shinichi Nishizawa, Yan-Shiun Wu, Jun Shiomi, Yih-Lang Li, Hidetoshi Onodera, "Pin Accessibility Evaluating Model for Improving Routability of VLSI Designs", IEEE International System-On-Chip Conference (SoCC), September 2017
  17. Hong-Yan Su, Shinichi Nishizawa, Yan-Shiun Wu, Jun Shiomi, Yih-Lang Li, Hidetoshi Onodera, "Computation of Pin Accessibility for Improving Routability of VLSI Designs", VLSI DESIGN/CAD SYMPOSIUM, August 2017.
  18. Takafuji Fujii, Shinichi Nishizawa, Kazuhito Ito, "Register-Bridge Architecture and its Application to Multiprocessor Systems, "Workshop on Synthesis And System Integration of Mixed Information technologies, October 2016.
  19. Tatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera, "Variation-Aware Flip-Flop Energy Optimization for Ultra Low Voltage Operation," IEEE International System-On-Chip Conference (SoCC), pp.17-22, September 2014, USA.
  20. Masahiro Kondo, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera, "A Standard Cell Optimization Method for Near-Threshold Voltage Operations," International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), September 2012.
  21. Shuichi Fujimoto, Islam A.K.M Mahfzul, Shinichi Nishizawa, Hidetoshi Onodera, "Extraction of Variability Sources from Within-die Random Delay Variation," International Workshop on Design for Manufacturability & Yield (DFM&Y), pp. 61-64, 2010/06, USA.
  22. Kyosuke Ito, Takahi Matsumoto, Shinichi Nishizawa Hiroki Sunagawa, Kazutoshi Kobayashi, Hidetoshi Onodera, "The Impact of RTN on Performance Fluctuation in CMOS Logic Circuits," International Reliability Physics Symposium (IRPS), pp. CR.5.1-CR.5.4, April 2011, USA.
  23. Kyosuke Ito, Takashi Matsumoto, Shinichi Nishizawa, Hiroki Sunagawa, Kazutoshi Kobayashi, Hidetoshi Onodera, "Modeling of Random Telegraph Noise under Circuit Operation - Simulation and Measurement of RTN-induced delay fluctuation," International Symposium on Quality Electronic Design (ISQED), pp. 22-27, March 2011, USA.
  24. Kyosuke Ito, Takashi Matsumoto, Shinichi Nishizawa, Hiroki Sunagawa, Kazutoshi Kobayashi, Hidetoshi Onodera, "Modeling of Random Telegraph Noise under Circuit Operation- Simulation and Measurement of RTN-induced Delay Fluctuation,", IEEE/ACM International Workshop on Variability Modeling and Characterization (VMC), October 2010, USA.

Domestic Conferences (22)

  1. 西澤真一, 木村晋二，"回帰分析を用いたフリップフロップのばらつき考慮化設計," ETNET，2025/03，鹿児島.
  2. 西澤真一, 木村晋二，"Double Diffusion Break FinFET プロセスにおける面積ペナルティを軽減するセル内トランジスタ再配置法"，デザインガイア，2024/11，大分.
  3. 西澤真一, 木村晋二，"オープンソースキャラクタライザのシミュレーション並列化"，DAシンポジウム，2024/08，鳥羽.
  4. 西澤真一、名倉徹，"オープンソース集積回路設計に向けたオープンソースキャラクタライザ"，DAシンポジウム，2022/08，鳥羽.
  5. 西澤真一、伊藤和人，"フリップフロップの記憶保持特性とIDDQテストを組み合わせたプロセスばらつき推定", VLSI設計技術研究会, 2020/03，沖縄(オンライン).
  6. 西澤真一, 伊藤和人, "セル内配線トラック数に応じた配線層の自動選択機能を備えたセルレイアウトジェネレータ", デザインガイア, 2018/12，広島.
  7. 西澤真一, 今野拓真, 伊藤和人, "フリップフロップの記憶保持特性を利用したトランジスタばらつきの推定", DAシンポジウム, 2017/08，石川.
  8. 西澤真一, 石原 亨, 小野寺秀俊, "電源電圧に応じてトランジスタサイズを最適化可能なセルライブラリの生成システム," DAシンポジウム, pp. 97-102, 2014/08, 下呂.
  9. 西澤真一, 石原 亨, 小野寺秀俊, "低電圧動作に向けたXOR論理ゲートの構成法の検討, " DAシンポジウム, pp.9-14, 2013/08, 下呂.
  10. 西澤真一, 石原亨, 小野寺秀俊, "低電圧動作に向けたPN比可変スタンダードセルライブラリの構成法とその評価", DAシンポジウム, pp.175-180, 2012/08, 下呂.
  11. 西澤真一, 小林和淑, 小野寺秀俊, "パッケージとの接続抵抗を考慮したチップ内電源ネットワークの構成手法", DAシンポジウム, pp. 45-50, 2011/08, 下呂.
  1. Xinyi Guo, Geguang Miao, Shinichi Nishizawa, Shinji Kimura, Takashi Sato，"Optimizing Prime Factorization Scalability via Quantum Annealing with Analytical and Pattern-Based Variable Reduction under Partial Constraints"，DAシンポジウム2024，2024/08，鳥羽.
  2. Mingtao Zhang, Ke Ma, Shinichi Nishizawa, Shinji Kimura, "Evaluation of Application-Independent Unbiased Approximate Multipliers for Quantized Convolutional Neural Networks", DAシンポジウム, 2023/08, 石川.
  3. 今井祐貴、西澤真一、伊藤和人，"LSIの最大消費電力を削減するスタック構造スタンダードセルライブラリ", VLSI設計技術研究会, 2020/03，沖縄(オンライン).
  4. 保坂 巧，西澤 真一，岸田 亮，松本 高士，小林 和淑, "単発DCストレス測定による負バイアス温度不安定性のAC特性を再現可能なモデル," デザインガイア, 2019/11，松山.
  5. 中鉢洸太, 西澤真一, 伊藤和人, "チャージポンプによる動的基板バイアス制御を用いた低電圧動作SRAMの検討", デザインガイア, 2018/12，広島.
  6. 深澤研人, 西澤真一, 伊藤和人, "トランジスタサイズを変えた記憶保持特性の異なるフリップフロップ群を利用したばらつき評価", デザインガイア, 2018/12，広島.
  7. 保坂巧，西澤真一，岸田亮，小林和淑，松本高士，坂本浩則，籔内美智太郎，熊代成孝，"65 nm FD-SOI における NBTI の逆方向基板バイアス依存性の評価", 電子情報通信学会 総合大会. 2018/03.
  8. 中鉢洸太, 西澤真一, 伊藤和人, "薄膜FDSOIトランジスタを用いた低電圧動作逆方向バイアス電圧生成回路", DAシンポジウム, 2017/08，石川.
  9. 中馬良兵、西澤真一、伊藤和人，"極低電圧動作を目指したD-Nwellレス細粒度基板バイアスSRAMビットセルの検討", DAシンポジウム, pp.20-25, 2016/09, 石川.
  10. 鎌苅竜也，西澤真一, 石原 亨, 小野寺秀俊, "製造ばらつきを考慮した極低電圧動作向けフリップフロップの設計手法," DAシンポジウム, pp. 91-96, 2014/08, 下呂.
  11. 竹下俊宏, 西澤真一, Islam A.K.M. Mahfuzul, 石原亨, 小野寺秀俊, "動作状況に応じた電源電圧と基板バイアスの同時調節によるLSIのエネルギー効率最大化", 電子情報通信学会 2014年総合大会, 2014/03, 新潟.
  12. 藤本秀一、Islam A.K.M. Mahfuzul、西澤真一、小野寺秀俊, "チップ内ばらつきの成分解析手法", DAシンポジウム, pp. 215-220, 2010/09, 下呂.

Magazines (1)

  1. 西澤真一, "研究会推薦博士論文速報 : 集積回路のエネルギー効率向上を目指した性能ばらつきの予測技術とセルライブラリの構築に関する研究," 情報処理学会 情報処理, Vol.56, No.9, 2015.

Invited Talks (2)

  1. Shinichi Nishizawa, "libretto: An open-source library characterizer for open-source VLSI design," Free Silicon Conference (FSiC)，2025/07, Frankfurt (Oder).
  2. 西澤真一、名倉徹，"ハードウェア設計のオープンソース化に向けたライブラリキャラクタライザの開発，" IEICE総合大会，2023/03, さいたま.
  3. 西澤真一, "集積回路設計を支える設計・製造協調最適設計", IEICE東北支部講演会, 2022/12, 弘前.

Others (10)

　
  1. Shinichi Nishizawa, "Development of a library characterizer for utilizing self-made cell libraries in open semiconductor design," RISC-V DAY TOKYO 2025 Spring, 2025/2
  2. 西澤真一，スタンダードセルレイアウト自動生成ツールの開発，第61回AIチップ設計拠点フォーラム，2024/7．
  3. Shinichi Nishizawa, "Standard Cell Structure and Transistor Reordering for Mitigating Area Penalty in Double Diffusion Break FinFET Process", talk at National Yang Ming Chiao Tung University, 2024/04, Hsinchu, Taiwan.
    4. 　
  4. 分担，ISSCC2024における研究開発動向，第57回AIチップ設計拠点フォーラム，2024/03．
  5. 西澤真一，設計・製造協調最適化とそのインターフェースとなるセルライブラリの最適化設計，第53回AIチップ設計拠点フォーラム，2023/11．
  6. 西澤真一，オープンソースライブラリキャラクタライザの開発，第3回オープンソースEDAフォーラム，2023/06，福岡.
  7. Shinichi Nishizawa, "Standard cell library design for design technology co-optimization", talk at National Yang Ming Chiao Tung University, 2023/04, Hsinchu, Taiwan.
  8. 今野拓真，西澤真一，伊藤和人，"フリップフロップの記憶保持特性を利用したトランジスタばらつきの解析", IPSJ LSIとシステムのワークショップ, 2017/05，東京.
  9. 西澤真一，伊藤和人, "貫通電流の電源電圧依存性を考慮したゲート遅延モデル," LSIとシステムのワークショップ, 2016/05, ポスター，東京.
  10. 西澤真一, 小野寺秀俊 "チップ内ばらつき成分の分析と評価", VDECデザイナーズフォーラム2011, 2011/05, 東京 .
  11. 西澤真一, "FPGAボードを用いたテスト環境", CREST DVLSI テスト構造フォーラム, 2010/03, 京都.

Honors (7)

  1. [学生の受賞] 情報処理学会 SLDM研究会 セッション特別賞 (2024/08/28), Mingtao Zhang, DAシンポジウム 2023.
  2. [学生の受賞] Best Paper Award (2023/09/06), Zekun Wang, Shinichi Nishizawa, Shinji Kimura, International Symposium on System-on-Chip Conference 2023.
  1. 電子情報通信学会 VLD研究会 デザインガイア・ポスター賞 (2024/11/13) (2024/11/13)：西澤真一, 木村晋二，"Double Diffusion Break FinFET プロセスにおける面積ペナルティを軽減するセル内トランジスタ再配置法"，デザインガイア 2024.
  2. 情報処理学会 SLDM研究会 優秀発表学生賞 (2015/8/26)：西澤真一，石原亨，小野寺秀俊，"電源電圧に応じてトランジスタサイズを最適化可能なセルライブラリの生成システム" ， DAシンポジウム 2014.
  3. 情報処理学会 コンピュータサイエンス領域奨励賞 (2013/8/21)：西澤真一，近藤正大，石原亨，小野寺秀俊，"低電圧動作に向けたPN比可変スタンダードセルライブラリの構成法とその評価 "，DAシンポジウム 2012.
  4. 情報処理学会 SLDM研究会 優秀発表学生賞 (2013/8/21)：西澤真一，近藤正大，石原亨，小野寺秀俊，"低電圧動作に向けたPN比可変スタンダードセルライブラリの構成法とその評価"，DAシンポジウム 2012.
  5. IEEE関西支部 学生研究奨励賞 (2013/2/12)：Shinichi Nishizawa and Hidetoshi Onodera, "Ring Oscillator with Calibration Circuit for Accurate On-Chip IR-drop Measurement", International Conference on Microelectronic Test Structures 2012.